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655 mhz low jitter clock generator ad9540 rev. a in for m a t i o n f u r n is h e d b y an al o g d e vice s is b e li ev e d to b e accu ra te a n d reli abl e . h o w e v e r , n o r e sp o n sibi lit y is as s u m e d by an al o g d e vices fo r i t s u s e , n o r fo r a n y i n fr i n g e m e nts of pate n t s or ot h e r r i g h ts o f th ir d par t ies th a t m a y r e su l t f r o m i t s use . s p e c i f ica t io n s su bj e c t t o c h an g e w i th o u t n o ti c e . n o l i c e n s e i s g r an t e d b y imp l ic a t io n o r o t h e r w i s e un d e r an y pa t e n t o r pa t e n t r i g h t s o f a n a l o g d e v i c e s . t r adem ar ks and r e g i st e r ed tr ad ema r ks ar e the p r o p er t y of the i r r e sp e c t i v e o w ne rs . o n e t e chnology way, p . o. b o x 91 06, nor w ood , ma 020 62- 910 6, u. s . a. t e l: 781. 329. 4 700 w w w . analog .c om fax: 781. 461. 31 13 ? 2006 a n alog de vices, i n c. al l r i ght s r e ser v ed . fea t ures ex c e llen t in trin sic jitt er per f or manc e 200 mh z phase frequenc y de tec t or inputs 655 mh z progr a mmable input divi ders f o r th e phase fr equenc y dete c t or (m, n) { m , n = 1 t o 16} (bypassable) p r ogr a mmable rf di vider (r) {r = 1, 2, 4, 8} ( b ypassable) 8 pr ogr a mmable phase/fr equenc y pr ofiles 400 msps int e r n al dds clock speed 48-bit fr eq uen c y tuning w o r d r e solution 14-bit pr ogr a mmable phase off s et 1.8 v sup p l y f o r de vic e oper a t ion 3.3 v sup p ly f o r i/o , cml driv e r , and char ge p u mp output s o f t ware c o ntr o lled pow e r- down 48-lea d lfcsp_ v q pack age p r ogr a mmable char ge pump curr en t (up t o 4 ma ) du al-mode pll lock det e c t 655 mh z cml - mode pecl - c ompliant output driv er applic a t io ns clock ing high per f ormanc e da ta c o n v er t e rs base sta t ion clock i ng ap pli c a t ions n e tw ork (son et/sd h ) clock i ng gigabit e t hern et ( g be) clock i ng instrumen t a t ion clock i ng cir c uits a g ile l o fr equenc y synthes i s a u t o motiv e r a dar f m chirp sour c e f o r r a dar and sc anning sy st ems t e st and m eas ur ement eq uip m ent a c oust o - optic de vic e driv ers func ti on a l bl ock di a g r a m avdd agnd dvdd dgnd cp_vdd cp_rset cp ref, amp refin refin clk1 clk1 charge pump phase frequency detector m divider n divider divider 1, 2, 4, 8 sync_in/status sync, pll lock sclk sdi/o sdo cs serial control port timing and control logic clk2 cp_out clk2 drv_rse t out0 cml out0 clk divclk s2 s1 s0 phase/ frequency profiles dds iout iout dac dac_rset 48 10 14 04947-001 ad9540 figure 1.
ad9540 rev. a | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 product overview ............................................................................. 3 specifications ..................................................................................... 4 loop measurement conditions .................................................. 8 absolute maximum ratings ............................................................ 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 12 typical application circuits .......................................................... 17 application circuit descriptions ............................................. 18 theory of operation ...................................................................... 19 pll circuitry .............................................................................. 19 cml driver ................................................................................. 19 dds and dac ............................................................................ 20 modes of operation ....................................................................... 21 selectable clock frequencies and selectable edge delay ..... 21 synchronization modes for multiple devices .............................. 21 serial port operation ..................................................................... 22 instruction byte .......................................................................... 23 serial interface port pin description ....................................... 23 msb/lsb transfers .................................................................... 23 register map and description ...................................................... 24 control register bit descriptions ............................................ 27 outline dimensions ....................................................................... 32 ordering guide .......................................................................... 32 revision history 2/06rev. 0 to rev. a changes to features section............................................................ 1 changes to applications section .................................................... 1 changes to functional block diagram.......................................... 1 changes to table 1............................................................................ 4 changes to typical application circuits section....................... 17 updates to ordering guide........................................................... 32 7/04revision 0: initial version
ad9540 rev. a | page 3 of 32 product overview the ad9540 is analog devices first dedicated clocking product specifically designed to support the extremely stringent clocking requirements of the highest performance data converters. the device features high performance pll (phase- locked loop) circuitry, including a flexible 200 mhz phase frequency detector and a digitally controlled charge pump current. the device also provides a low jitter, 655 mhz cml- mode, pecl-compliant output driver with programmable slew rates. external vco rates up to 2.7 ghz are supported. extremely fine tuning resolution (steps less than 2.33 hz) is another feature supported by this device. information is loaded into the ad9540 via a serial i/o port that has a device write speed of 25 mbps. the ad9540 frequency divider block can also be programmed to support a spread spectrum mode of operation. the ad9540 is specified to operate over the extended automotive range of ?40c to +85c.
ad9540 rev. a | page 4 of 32 specifications avdd = dvdd = 1.8 v 5%; dvdd_i/o = cp_vdd = 3.3 v 5% (@ t a = 25c), dac_r set = 3.92 k?, cp_r set = 3.09 k?, drv_r set = 4.02 k?, unless otherwise noted. table 1. parameter min typ max unit test conditions/comments total system jitter and phase noise for 105 mhz adc clock generation circuit converter limiting jitter 1 720 f s rms resultant signal-to-noise ratio (snr) 59.07 db phase noise of fundamental @ 10 hz offset 80 dbc/hz @ 100 hz offset 92 dbc/hz @ 1 khz offset 101 dbc/hz @ 10 khz offset 110 dbc/hz @ 100 khz offset 147 dbc/hz 1 mhz offset 153 dbc/hz total system phase noise for 210 mhz adc clock generation circuit phase noise of fundamental @ 10 hz offset 79.2 dbc/hz @ 100 hz offset 86 dbc/hz @ 1 khz offset 95 dbc/hz @ 10 khz offset 105 dbc/hz @ 100 khz offset 144 dbc/hz @ 1 mhz offset 151 dbc/hz total system time jitter for clocks 155.52 mhz clock 581 f s rms 12 khz to 1.3 mhz bandwidth 622.08 mhz clock 188 f s rms 12 khz to 5 mhz bandwidth rf divider/cml driver equivalent intrinsic time jitter f in = 414.72 mhz, f out = 51.84 mhz 136 f s rms r = 8, bw = 12 khz to 400 khz f in = 1244.16 mhz, f out = 155.52 mhz 101 f s rms r = 8, bw = 12 khz to 1.3 mhz f in = 2488.32 mhz, f out = 622.08 mhz 108 f s rms r = 4, bw = 12 khz to 5 mhz rf divider/cml driver residual phase noise f in = 81.92 mhz, f out = 10.24 mhz rf divider r = 8 @ 10 hz 120 dbc/hz @ 100 hz 128 dbc/hz @ 1 khz 137 dbc/hz @ 10 khz 145 dbc/hz @ 100 khz 150 dbc/hz 1 mhz 153 dbc/hz f in = 983.04 mhz, f out = 122.88 mhz rf divider r = 8 @ 10 hz 115 dbc/hz @ 100 hz 125 dbc/hz @ 1 khz 132 dbc/hz @ 10 khz 142 dbc/hz @ 100 khz 146 dbc/hz @ 1 mhz 151 dbc/hz >3 mhz 153 dbc/hz
ad9540 rev. a | page 5 of 32 parameter min typ max unit test conditions/comments f in = 1966.08 mhz, f out = 491.52 mhz rf divider r = 4 @ 10 hz 105 dbc/hz @ 100 hz 112 dbc/hz @ 1 khz 122 dbc/hz @ 10 khz 130 dbc/hz @ 100 khz 141 dbc/hz @ 1 mhz 144 dbc/hz >3 mhz 146 dbc/hz f in = 2488 mhz, f out = 622 mhz rf divider r = 4 @ 10 hz 100 dbc/hz @ 100 hz 108 dbc/hz @ 1 khz 115 dbc/hz @ 10 khz 125 dbc/hz @ 100 khz 135 dbc/hz @ 1 mhz 140 dbc/hz 3 mhz 142 dbc/hz phase frequency detector/charge pump refin input input frequency 2 m set to divide by at least 4 655 mhz m bypassed 200 mhz input voltage levels 200 450 600 mv p-p input capacitance 10 pf input resistance 1500 ? clk2 input input frequency n set to divide by at least 4 655 mhz n bypassed 200 mhz input voltage levels 200 450 600 mv p-p input capacitance 10 pf input resistance 1500 ? charge pump source/sink maximum current 4 ma charge pump source/sink accuracy 5 % charge pump source/sink matching 2 % charge pump output compliance range 3 0.5 cp_vdd ? 0.5 v status drive strength 2 ma phase frequency detector noise floor @ 50 khz pfd frequency 148 dbc/hz @ 2 mhz pfd frequency 133 dbc/hz @ 100 mhz pfd frequency 116 dbc/hz @ 200 mhz pfd frequency 113 dbc/hz rf divider (clk1 ) input section (r) rf divider input range 1 2700 mhz dds sysclk not to exceed 400 msps input capacitance (dc) 3 pf input impedance (dc) 1500 ? input duty cycle 42 50 58 % input power/sensitivity ?10 +4 dbm single-ended, into a 50 ? load 4 input voltage level 200 1000 mv p-p
ad9540 rev. a | page 6 of 32 parameter min typ max unit test conditions/comments cml output driver (out0) differential output voltage swing 5 720 mv 50 ? load to supply, both lines maximum toggle rate 655 common-mode output voltage 1.75 v output duty cycle 42 58 % output current continuous 6 7.2 ma rising edge surge 20.9 ma falling edge surge 13.5 ma output rise time 250 ps 100 ? terminated, 5 pf load output fall time 250 ps 100 ? terminated, 5 pf load logic inputs (sdi/o, i/o_reset, reset, i/o_update, s0, s1, s2, sync_in) v ih , input high voltage 2.0 v v il , input low voltage 0.8 v i inh , i inl , input current 1 5 a c in , maximum input capacitance 3 pf logic outputs (sdo, sync_out, status) 7 v oh , output high voltage 2.7 v v oh , output low voltage 0.4 v i oh 100 a i ol 100 a power consumption total power consumed, all functions on 400 mw i(avdd) 85 ma i(dvdd) 45 ma i(dvdd_i/o) 20 ma i(cp_vdd) 15 ma power-down mode 80 mw wake-up time (from power-down mode) digital power-down 12 ns control function register 1[7] dac power-down 7 s control function register 3[39] rf divider power-down 400 ns control function register 2[23] clock driver power-down 6 s control function register 2[20] charge pump full power-down 10 s control function register 2[4] charge pump quick power-down 150 ns control function register 2[3] crystal oscillator (on refin input) operating range 20 25 30 mhz residual phase noise (@ 25 mhz) @ 10 hz offset 95 dbc/hz @ 100 hz offset 120 dbc/hz @ 1 khz offset 140 dbc/hz @ 10 khz offset 157 dbc/hz @ 100 khz offset 164 dbc/hz >1 mhz offset 168 dbc/hz digital timing specifications cs to sclk setup time, t pre 6 ns period of sclk (write), t sclkw 40 ns period of sclk (read), t sclkr 400 ns serial data setup time, t dsu 6.5 ns serial data hold time, t dhd 0 ns data valid time, t dv 40 ns
ad9540 rev. a | page 7 of 32 parameter min typ max unit test conditions/comments i/o_update to sync_out setup time 7 ns ps[2:0> to sync_out setup time 7 ns latencies/pipeline delays i/o_update to dac frequency change 33 sysclk cycles i/o_update to dac phase change 33 sysclk cycles ps[2:0] to dac frequency change 29 sysclk cycles ps[2:0] to dac phase change 29 sysclk cycles i/o_update to cp_out scaler change 4 sysclk cycles i/o_update to frequency accumulator step size change 4 sysclk cycles dac output characteristics resolution 10 bits full-scale output current 10 15 ma gain error ?10 +10 % f s output offset 0.6 a output capacitance 5 pf voltage compliance range avdd ? 0.50 avdd + 0.50 wideband sfdr (dc to nyquist) 10 mhz analog out 65 dbc 40 mhz analog out 62 dbc 80 mhz analog out 57 dbc 120 mhz analog out 56 dbc 160 mhz analog out 54 dbc narrow-band sfdr 10 mhz analog out (1 mhz) 83 dbc 10 mhz analog out (250 khz) 85 dbc 10 mhz analog out (50 khz) 86 dbc 40 mhz analog out (1 mhz) 82 dbc 40 mhz analog out (250 khz) 84 dbc 40 mhz analog out (50 khz) 87 dbc 80 mhz analog out (1 mhz) 80 dbc 80 mhz analog out (250 khz) 82 dbc 80 mhz analog out (50 khz) 86 dbc 120 mhz analog out (1 mhz) 80 dbc 120 mhz analog out (250 khz) 82 dbc 120 mhz analog out (50 khz) 84 dbc 160 mhz analog out (1 mhz) 80 dbc 160 mhz analog out (250 khz) 82 dbc 160 mhz analog out (50 khz) 84 dbc dac residual phase noise 19.7 mhz f out @ 10 hz offset 122 dbc/hz @ 100 hz offset 134 dbc/hz @ 1 khz offset 143 dbc/hz @ 10 khz offset 150 dbc/hz @ 100 khz offset 158 dbc/hz >1 mhz offset 160 dbc/hz
ad9540 r e v. a | pa ge 8 o f 3 2 p a r a me t e r m i n t y p ma x u n i t t e s t c o ndition s /c ommen t s 51.84 mh z f ou t @ 10 h z o f f s et 110 dbc/h z @ 100 h z o f f s et 121 dbc/h z @ 1 kh z o f f s et 135 dbc/h z @ 10 kh z o f f s et 142 dbc/h z @ 100 kh z o f f s e t 148 dbc/h z > 1 mh z o f f s et 153 dbc/h z 105 mh z analog o ut @ 10 h z o f f s et 105 dbc/h z @ 100 h z o f f s et 115 dbc/h z @ 1 kh z o f f s et 126 dbc/h z @ 10 kh z o f f s et 132 dbc/h z @ 100 kh z o f f s e t 140 dbc/h z >1 mh z o f f s et 145 dbc/h z 155.52 mh z analog o ut @ 10 h z o f f s et 100 dbc/h z @ 100 h z o f f s et 112 dbc/h z @ 1 kh z o f f s et 123 dbc/h z @ 10 kh z o f f s et 131 dbc/h z @ 100 kh z o f f s e t 138 dbc/h z >1 mh z o f f s et 144 dbc/h z 1 the snr of a 14-bit adc was measur ed with an encode rate of 105 msps a n d an ain of 170 mhz. the r e su ltant snr was known to b e l imited by the jitter of the cl oc k, no t by the no is e o n the a i n s i gnal . from this s nr val u e , t h e jitte r af f e cting t h e me as ure m e nt can be back cal c ul ate d . 2 d r i v i n g t h e r e fin i n put buffer. th e cr y s t a l o s ci l l a t or s e ct i o n of t h i s i n put st a g e per f orm s up t o o n ly 30 mh z. 3 th e ch a rge pum p out p ut com p li a n ce ra n g e i s fun c t i on a l l y 0.2 v t o (c p_ vd d ? 0.2 v). th e va lu e l i st ed h e r e i s t h e c o m p li a n ce ra n ge for 5% matching. 4 the input impedance of the clk1 input is 1500 ?. how e v e r, to provide mat ching on the cloc k line, an external 50 ? loa d is used . 5 mea s ure d a s pea k - t o- pea k bet w een d a c out p ut s. 6 for a 4.02 k? re si st or from d r v _r set t o gn d . 7 a ssum e s a 1 m a l o a d . loop measurement conditions 622 mhz oc-1 2 clock v c o = s i r e nza 190-640t ref e r e n c e = w e nze l 500-10116 (30.3 mh z) l o o p f i lt er = 10 khz b w , 60 phas e m a rg i n c1 = 170 nf , r1 = 14.4 ?, c2 = 5.11 f , r2 = 89 .3 ?, c3 omi t t e d cp_o ut = 4 ma (s caler = 8) r = 2, m = 1, n = 1 105 mhz conv erter clock v c o = s i r e nza 190-845t ref e r e n c e = w e nze l 500-10116 (30.3 mh z) l o o p f i lt er = 10 khz b w , 45 phas e m a rg i n c1 = 117 nf , r1 = 28 ?, c2 = 1.6 f , r2 = 57.1 ?, c3 = 53.4 nf cp_o ut = 4 ma (s caler = 8) r = 8, m = 1, n = 1 c1 c3 input output c2 r1 r2 04947- 041 figure 2. gen e r i c l oop f i lter
ad9540 r e v. a | pa ge 9 o f 3 2 absolute maximum ra tings table 2. p a r a me t e r r a t i n g analog sup p ly v o ltage ( a vdd) 2 v digital sup p ly v o ltage ( d vdd) 2 v dig i tal i/ o supply v o ltage (dvdd_i/o ) 3.6 v charge p u mp sup p ly v o ltage (c p _ v d d) 3.6 v m a ximum digital i n put v o ltage ?0.5 v to dvdd_i/o + 0.5 v stor age t e mpera tur e r a nge ?65c to +150c o p era t ing t e mper a tur e r a nge ?40c to +125c l e ad t e mper a tur e (sol dering 10 s e c) 300c junc tion t e mpe r a tur e 150c ther mal r e sistanc e ( ja ) 2 6 c / w s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im pl ie d . e x p o sur e t o a b s o l u te max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . esd caution esd (elec t r o sta t ic dischar g e) sensitiv e devic e . e l ec tr osta tic charges as high as 4000 v r e adily ac cumula te on the human body and t e st eq uipmen t and can dischar g e with out det e c t ion. although this pr oduc t f e a tur es pr oprietar y esd pr ot ec tion cir c uitr y , permanen t dama ge may oc cur on dev i c e s sub j ec ted to high ener gy elec tr o s ta tic di scharge s . theref or e , proper esd pr ecautio n s a r e r e c o m m ended to a v oid per f or man c e degrada t ion or l o ss of func tiona l it y .
ad9540 rev. a | page 10 of 32 pin conf igura t ion and fu nction descriptions 13 14 15 16 17 18 19 20 21 22 23 24 sdo sdi/o sclk cs dvdd_ i/o sync_ out sync_in/status i/o_update s0 s1 s2 dgnd 48 47 46 45 44 43 42 41 40 39 38 37 avdd dac_ rse t drv_ r set cp_rset avdd agnd clk2 clk2 refin refin avdd agnd 1 2 3 4 5 6 7 8 9 10 11 12 agnd avdd agnd avdd iout iout avdd agnd i/o_reset reset dvdd dgnd cp_vdd agnd out0 out0 cp_vdd agnd clk1 clk1 avdd agnd dvdd 35 cp_out 36 34 33 32 31 30 29 28 27 26 25 ad9540 top view (not to scale) pin 1 indicator 04947- 047 figure 3. 48-lead l f csp pin conf iguration ta ble 3. pi n f u nct i on d e s c ri pt i o ns p i n no . m n emonic description 1, 3, 8, 26, 30, 34, 37, 43, a g n d a n a l o g ground . 2, 4, 7, 27, 38, 44, 48 a v dd analog c o r e supply (1.8 v ) . 5 iout d a c analog o u t p ut. 6 iout d a c analog c o mplemen t ar y o utput. 9 i / o _ r e s e t r e sets the ser i al por t when sync hr oni z a t io n is lost in c o mmunic a tions but does not r e set the devic e itself (ac t iv e high). when not being used , this pin should be f o r c ed lo w , because it floa ts to the thr e shold v a lue . 10 rese t m a ster r e set. clears al l ac cumul a tors a n d r e tur ns all r e gister s to their default v a lues (ac t iv e high). 11, 25 dvdd dig i tal c o r e supply (1.8 v ) . 12, 24 dgnd dig i tal gr ound . 13 sdo serial da ta o utput. u s ed only when the d evic e is pr ogr a mmed f o r 3- w i r e s e rial da ta mode . 1 4 s d i / o serial da ta i n put/ o utput. when the par t is pr ogrammed f o r 3-wi r e ser i al d a ta mode , this is inpu t only ; in 2- wir e mode , it ser v es as both the inpu t and output. 15 sclk s e rial da ta clock . p r o v ides the c l ock s i gnal f o r t h e ser i al da ta p o r t . 16 cs a c tiv e l o w sign al tha t enable s shar ed s e r i al bu ses . whe n brough t high, the ser i al por t igno r e s the ser i al d a ta cl ock s . 17 dvdd_i/o dig i tal i n ter f ac e supply (3.3 v ) . 18 sy nc_out synchr oniz a t io n clock o utput. 1 9 s y nc_in/st a t u s bidir e c t ion a l dual f u nc tion p i n. d e pending on devi c e pr ogr a m ming , this pin is either the dir e c t d i g i t a l s y nt h e s i z e r s ( d d s ) s y nchr oniza t ion input (a llo ws alignmen t of mu lt iple su bclocks), or t h e pll lock detec t out p ut sig n al . 2 0 i / o _ u p d a t e t h is input pin, when set high, t r ansf ers the da ta fr om the i/o b u ff ers to the in ter n al r e gi sters o n the r i sing edge of th e in ter n al sy nc _clk , which can be obser v e d on sy nc_out .
ad9540 rev. a | page 11 of 32 pin no. mnemonic description 21, 22, 23 s0, s1, s2 clock frequency and delay select pins. these pi ns specify one of eight clock frequency/delay profiles. 28 clk1 rf divider and internal clock complementary input. 29 clk1 rf divider and internal clock input. 31, 35 cp_vdd charge pump and cml driver supply pin. 3.3 v analog (clean) supply. 32 out0 cml driver complementary output. 33 out0 cml driver output. 36 cp_out charge pump output. 39 refin phase frequency detector reference input. 40 refin phase frequency detector reference complementary input. 41 clk2 phase frequency detector oscillator (feedback) complementary input. 42 clk2 phase frequency detector oscillator (feedback) input. 45 cp_rset charge pump current set. program charge pump current with a resistor to agnd. 46 drv_rset cml driver output current set. program cml output current with a resistor to agnd. 47 dac_rset dac output current set. program dac output current with a resistor to agnd. paddle exposed paddle the exposed paddle on this package is an electric al connection as well as a thermal enhancement. in order for the device to function properly, the paddle must be attached to analog ground.
ad9540 rev. a | page 12 of 32 typical perf orm ance cha r acte ristics 04947-003 center 10.1mhz 5khz/ span 50khz ref lvl 0dbm delta 1 [t1] ? 85.94db ?2.10420842khz rbw vbw swt rf att unit 100hz 100hz 25s 20db db 1 ap a ?2 0 ?4 0 0 ?6 0 ?3 0 ?5 0 ?1 0 ?7 0 ?8 0 ?9 0 ?100 1 1 f i gure 4. d a c p e r f ormance: 400 ms ps clock , 10 m h z f ou t , 5 0 k h z spa n 04947-004 center 10.1mhz 100khz/ span 1mhz ref lvl 0dbm delta 1 [t1] ? 86.03db ?368.73747495khz rbw vbw swt rf att unit 500hz 500hz 20s 20db db 1 ap a ?2 0 ?4 0 0 ?6 0 ?3 0 ?5 0 ?1 0 ?7 0 ?8 0 ?9 0 ?100 1 1 f i gure 5. d a c p e r f ormance: 400 ms ps clock , 10 m h z f ou t , 1 mh z span 04947-005 start 0hz 20mhz/ stop 200mhz ref lvl 0dbm delta 1 [t1] ? 64.54db 100.20040080mhz rbw vbw swt rf att unit 10khz 10khz 5s 20db db 1 ap a ?2 0 ?4 0 0 ?6 0 ?3 0 ?5 0 ?1 0 ?7 0 ?8 0 ?9 0 ?100 1 1 f i gure 6. d a c p e r f ormance: 400 ms ps clock , 10 m h z f ou t , 2 0 0 m h z sp an 04947-006 center 40.1mhz 5khz/ span 50khz ref lvl 0dbm delta 1 [t1] ? 84.94db 2.10420842khz rbw vbw swt rf att unit 100hz 100hz 25s 20db db 1 ap a ?2 0 ?4 0 0 ?6 0 ?3 0 ?5 0 ?1 0 ?7 0 ?8 0 ?9 0 ?100 1 1 fi g u r e 7 . d a c pe r f o r m a n c e : 400 msp s cl oc k , 40 m h z f ou t , 5 0 k h z spa n 04947-007 center 40.1mhz 100khz/ span 1mhz ref lvl 0dbm delta 1 [t1] ? 80.17db ?200.40080160khz rbw vbw swt rf att unit 500hz 500hz 20s 20db db 1 ap a ?2 0 ?4 0 0 ?6 0 ?3 0 ?5 0 ?1 0 ?7 0 ?8 0 ?9 0 ?100 1 1 fi g u r e 8 . d a c pe r f o r m a n c e : 400 msp s cl oc k , 40 m h z f ou t , 1 mh z span 04947-008 start 0hz 20mhz/ stop 200mhz ref lvl 0dbm delta 1 [t1] ? 61.61db 100.20040080mhz rbw vbw swt rf att unit 10khz 10khz 5s 20db db 1 ap a ?2 0 ?4 0 0 ?6 0 ?3 0 ?5 0 ?1 0 ?7 0 ?8 0 ?9 0 ?100 1 1 fi g u r e 9 . d a c pe r f o r m a n c e : 400 msp s cl oc k , 40 m h z f ou t , 2 0 0 m h z sp an (n yquist)
ad9540 rev. a | page 13 of 32 04947-009 center 100.1mhz 5khz/ span 50khz ref lvl 0dbm delta 1 [t1] ? 83.72db ?2.70541082khz rbw vbw swt rf att unit 100hz 100hz 25s 20db db 1 ap a ?2 0 ?4 0 0 ?6 0 ?3 0 ?5 0 ?1 0 ?7 0 ?8 0 ?9 0 ?100 1 1 f i gur e 1 0 . d a c p e r f o r m a nc e : 40 0 msps clo c k , 10 0 m h z f ou t , 5 0 k h z sp an 04947-010 center 100.1mhz 100khz/ span 1khz ref lvl 0dbm delta 1 [t1] ? 56.47db ?400.80160321khz rbw vbw swt rf att unit 500hz 500hz 20s 20db db 1 ap a ?2 0 ?4 0 0 ?6 0 ?3 0 ?5 0 ?1 0 ?7 0 ?8 0 ?9 0 ?100 1 1 f i gur e 1 1 . d a c p e r f o r m a nc e : 40 0 msps clo c k , 10 0 m h z f ou t , 1 m h z sp an 04947-011 start 0hz 20mhz/ stop 200mhz ref lvl 0dbm delta 1 [t1] ? 48.71db ?400.80160321khz rbw vbw swt rf att unit 10khz 10khz 5s 20db db 1 ap a ?2 0 ?4 0 0 ?6 0 ?3 0 ?5 0 ?1 0 ?7 0 ?8 0 ?9 0 ?100 1 1 f i gur e 1 2 . d a c p e r f o r m a nc e : 40 0 msps clo c k , 10 0 m h z f ou t , 2 00 m h z sp an 04947-012 center 159.5mhz 5khz/ span 50khz ref lvl 0dbm delta 1 [t1] ? 85.98db ?2.90581162khz rbw vbw swt rf att unit 100hz 100hz 25s 20db db 1 ap a ?2 0 ?4 0 0 ?6 0 ?3 0 ?5 0 ?1 0 ?7 0 ?8 0 ?9 0 ?100 1 1 f i gur e 1 3 . d a c p e r f o r m a nc e : 40 0 msps clo c k , 16 0 m h z f ou t , 5 0 k h z sp an 04947-013 center 159.5mhz 100khz/ span 1mhz ref lvl 0dbm delta 1 [t1] ? 82.83db 262.52505010khz rbw vbw swt rf att unit 500hz 500hz 20s 20db db 1 ap a ?2 0 ?4 0 0 ?6 0 ?3 0 ?5 0 ?1 0 ?7 0 ?8 0 ?9 0 ?100 1 1 f i gur e 1 4 . d a c p e r f o r m a nc e : 40 0 msps clo c k , 16 0 m h z f ou t , 1 m h z sp an 04947-014 start 0hz 20mhz/ stop 200mhz ref lvl 0dbm delta 1 [t1] ? 54.90db ? 78.55711423mhz rbw vbw swt rf att unit 10khz 10khz 5s 20db db 1 ap a ?2 0 ?4 0 0 ?6 0 ?3 0 ?5 0 ?1 0 ?7 0 ?8 0 ?9 0 ?100 1 1 f i gur e 1 5 . d a c p e r f o r m a nc e : 40 0 msps clo c k , 16 0 m h z f ou t , 2 00 m h z sp an
ad9540 rev. a | page 14 of 32 frequency (hz) l(f) (dbc / h z) 0 ?10 ?20 ?30 ?40 ?60 ?50 ?70 ?80 ?90 ? 100 ? 110 ? 130 ? 120 ? 140 ? 160 ? 150 ? 170 10 1k 100 10k 100k 1m 04947-023 f i g u re 16. dds /da c r e s i dual phas e n o is e 40 0 m h z c l o c k , 19 . 7 m h z o u t p ut frequency (hz) l(f) (dbc / h z) 0 ?10 ?20 ?30 ?40 ?60 ?50 ?70 ?80 ?90 ? 100 ? 110 ? 130 ? 120 ? 140 ? 160 ? 150 ? 170 10 1k 100 10k 100k 10m 1m 04947-024 f i g u re 17. dds /da c r e s i dual phas e n o is e 40 0 m h z c l o c k , 51 . 84 m h z o u t p ut frequency (hz) l(f) (dbc / h z) 0 ?10 ?20 ?30 ?40 ?60 ?50 ?70 ?80 ?90 ? 100 ? 110 ? 130 ? 120 ? 140 ? 160 ? 150 ? 170 10 1k 100 10k 100k 10m 1m 04947-025 f i g u re 18. dds /da c r e s i dual phas e n o is e 40 0 m h z c l o c k , 10 5.3 m h z o u t p ut frequency (hz) l(f) (dbc / h z) 0 ?10 ?20 ?30 ?40 ?60 ?50 ?70 ?80 ?90 ? 100 ? 110 ? 130 ? 120 ? 140 ? 160 ? 150 ? 170 10 1k 100 10k 100k 10m 1m 04947-026 f i g u re 19. dds /da c r e s i dual phas e n o is e 40 0 m h z c l o c k , 15 5.5 2 m h z o u t p ut frequency (hz) l(f) (dbc / h z) 0 ?10 ?20 ?30 ?40 ?60 ?50 ?70 ?80 ?90 ? 100 ? 110 ? 130 ? 120 ? 140 ? 160 ? 150 ? 170 10 1k 100 10k 100k 1m 2m 04947-0-027 f i gure 20. r f d i v i d e r and c m l d r iver r e s i dua l p h ase n o is e (8 1. 92 mh z in , 1 0 . 2 4 mh z o u t) frequency (hz) l(f) (dbc / h z) 0 ?10 ?20 ?30 ?40 ?60 ?50 ?70 ?80 ?90 ? 100 ? 110 ? 130 ? 120 ? 140 ? 160 ? 150 ? 170 10 1k 100 10k 100k 1m 2m 04947-0-028 f i gure 21. r f d i v i d e r and c m l d r iver r e s i dua l p h a s e no i s e (157 .6 mhz in, 19 .7 mh z out)
ad9540 rev. a | page 15 of 32 frequency (hz) l(f) (dbc / h z) 0 ?10 ?20 ?30 ?40 ?60 ?50 ?70 ?80 ?90 ? 100 ? 110 ? 130 ? 120 ? 140 ? 160 ? 150 ? 170 10 1k 100 10k 100k 10m 1m 04947-029 f i gure 22. r f d i v i d e r and c m l d r iver r e s i dua l p h a s e no i s e (410 .4 mhz in, 51 .3 mh z out) frequency (hz) l(f) (dbc / h z) 0 ?10 ?20 ?30 ?40 ?60 ?50 ?70 ?80 ?90 ? 100 ? 110 ? 130 ? 120 ? 140 ? 160 ? 150 ? 170 10 1k 100 10k 100k 10m 1m 04947-030 f i gure 23. r f d i v i d e r and c m l d r iver r e s i dua l p h a s e no i s e (842 .4 mhz in, 105 .3 mhz out) frequency (hz) l(f) (dbc / h z) 0 ?10 ?20 ?30 ?40 ?60 ?50 ?70 ?80 ?90 ? 100 ? 110 ? 130 ? 120 ? 140 ? 160 ? 150 ? 170 10 1k 100 10k 100k 10m 1m 04947-031 f i gure 24. r f d i v i d e r and c m l d r iver r e s i dua l p h a s e no i s e (983 .04 mh z in, 12 2.88 m h z out) frequency (hz) l(f) (dbc / h z) 0 ?10 ?20 ?30 ?40 ?60 ?50 ?70 ?80 ?90 ? 100 ? 110 ? 130 ? 120 ? 140 ? 160 ? 150 ? 170 10 1k 100 10k 100k 10m 1m 04947-032 f i gure 25. r f d i v i d e r and c m l d r iver r e s i dua l p h a s e no i s e (124 0 mhz in, 155 mh z o u t) frequency (hz) l(f) (dbc / h z) 0 ?10 ?20 ?30 ?40 ?60 ?50 ?70 ?80 ?90 ? 100 ? 110 ? 130 ? 120 ? 140 ? 160 ? 150 ? 170 10 1k 100 10k 100k 10m 1m 04947-033 f i gure 26. r f d i v i d e r and c m l d r iver r e s i dua l p h a s e no i s e (168 0 mhz in, 210 mh z o u t) frequency (hz) l(f) (dbc / h z) 0 ?10 ?20 ?30 ?40 ?60 ?50 ?70 ?80 ?90 ? 100 ? 110 ? 130 ? 120 ? 140 ? 160 ? 150 ? 170 10 1k 100 10k 100k 10m 1m 04947-034 f i gure 27. r f d i v i d e r and c m l d r iver r e s i dua l p h as e n o is e (1 9 66. 08 m h z in, 49 1. 52 m h z o u t )
ad9540 rev. a | page 16 of 32 frequency (hz) l(f) (dbc / h z) 0 ?10 ?20 ?30 ?40 ?60 ?50 ?70 ?80 ?90 ? 100 ? 110 ? 130 ? 120 ? 140 ? 160 ? 150 ? 170 10 1k 100 10k 100k 10m 1m 04947-035 f i gure 28. r f d i v i d e r and c m l d r iver r e s i dua l p h a s e no i s e (248 8 mhz in, 622 mh z o u t) frequency (hz) l(f) (dbc / h z) 0 ?10 ?20 ?30 ?40 ?60 ?50 ?70 ?80 ?90 ? 100 ? 110 ? 130 ? 120 ? 140 ? 160 ? 150 ? 180 ? 170 10 1k 100 10k 100k 1m 20m 04947-0-036 f i gure 29. t o t a l s y s t em p h as e n o is e f o r 1 0 5 mh z co n v e r ter c l o c k frequency (hz) l(f) (dbc / h z) 0 ?10 ?20 ?30 ?40 ?60 ?50 ?70 ?80 ?90 ? 100 ? 110 ? 130 ? 120 ? 140 ? 160 ? 150 ? 180 ? 170 10 1k 100 10k 100k 1m 20m 04947-0-037 f i gure 30. t o t a l s y s t em p h as e n o is e f o r 2 1 0 mh z co n v e r ter c l o c k frequency (hz) l(f) (dbc / h z) 0 ?10 ?20 ?30 ?40 ?60 ?50 ?70 ?80 ?90 ? 100 ? 110 ? 130 ? 120 ? 140 ? 160 ? 150 ? 180 ? 170 10 1k 100 10k 100k 1m 20m 04947-0-038 f i g u re 31. t o t a l sy s t em p h as e n o is e f o r 6 2 2 m h z o c -1 2 c l ock
ad9540 rev. a | page 17 of 32 typical applica t ion circuits da c refin clk2 cp_out dds n m r lpf vco cml driver phase frequency detector/charge pump 25mhz crystal 400mhz clock1 clock1 ad9540 04947-042 lpf adcmp563 fi gur e 32 . dual cloc k co nfi g ur a t i o n da c c harg e pump refin clk2 dds n m r lpf vco cml driver phase frequency detector external reference 622mhz clock1 clock2 ad9540 04947-043 adcmp563 figure 33. optical networking c l ock refin clk2 cp_out dds r vco ad9540 04947-044 lpf lpf da c fig u re 3 4 fr act i on al-d iv ide r l oop cha rge pump refin clk2 n vco dds phase frequency detector 04947-045 lpf lpf dac ad9540 figure 3 5 . d i r ect u p conv e r sio n of dd s output spectr u m
ad9540 rev. a | page 18 of 32 04947-046 refin clk2 cp_out dds r vco ad9540 lpf dac n cml driver 2.5ghz tone 8-level fsk (fc = 100mhz) bpf bpf 25mhz crystal figure 36. ism ban d modu lato r (lo & baseb a nd ge ner a tion) applic ati o n circuit d e scripti o n s dual c l o c k c o n f igura t io n i n this lo o p , m = 1, n = 16, a n d r = 4. the d d s (dir ec t dig i tal syn t h e sizer) t u nin g w o r d is als o eq ual t o , s o t h a t t h e f r eq uen c y o f cl o c k1 e q uals t h e f r eq uen c y o f cl o c k 1. p h as e ad j u s t m e n t s i n t h e dds p r o v ide 14- b i t pr og ra mma b l e r i sin g edg e dela y ca p a b i l i ty o f clock1? with respect to cl o c k1 (s e e f i gur e 32). o p ti c a l n e twor k i n g c l o c k this is t h e ad9 540 co nf igur ed as a n o p tical n e tw o r kin g c l o c k. the lo o p can be us ed t o g e nera te a 622 mh z c l o c k f o r o c 12. the dds can b e p r og ra mm e d to o u t p u t 8 khz t o s e r v e as a b a s e re f e re nc e f o r ot he r c i rc u i t s i n t h e s u b s y s te m ( s e e f i g u re 3 3 ) . fraction al-div id er loop this loop offers the precise frequency div i sio n (48-b i t ) of the dds i n the fee d bac k pa th as well as th e frequency swee ping cap a b i li ty of the dds. programmi n g t h e dds to sw eep f r om 24 mhz to 25 mhz sw eeps the output of the vco from 2.7 ghz to 2.6 ghz. the reference in this c a se is a simple crystal (see figure 34). direct upco nversion the ad9540 is configured to use the dds as a precision reference to the pll. since the vco is <655 m h z, it can be fed straig ht i n to t h e phase freque nc y detector fee d b a ck. lo a n d ba s e ba nd mo dula t i on genera t i on using the ad9 540 pll sectio n to generate lo and the dds portion to gene rate a modul a te d ba seb a nd, t h is circuit uses an ex ternal m i x e r t o perfo r m so me simple mo du la tio n at rf ism ba nd fr eque nci e s (see f i gur e 3 6 ).
ad9540 rev. a | page 19 of 32 theor y of opera tion pll circuitry the ad9540 inc l udes a n rf divider (divide-b y -r), a 48-b i t dds co r e , a 14- b i t p r og ra mmab l e d e l a y ad j u st m e n t , a 10- b i t d a c (di g i t al- t o- a n alog co n v er t e r), a p h a s e f r eq uen c y d e t e c t o r , an d a pro g r a m m a bl e ou tput c u r r e n t c h ar g e pu m p . inc o r p or a t - in g t h es e b l o c ks t o g e t h er , us ers ca n g e n e ra t e ma n y us ef u l cir c ui ts fo r c l o c k syn t h e sis. a fe w sim p le exam ples a r e s h o w n in t h e t y pical p e r f o r ma n c e c h a r ac t e r i s t ics s e c t ion. the rf d i v i der accep t s dif f er en t i a l o r sing le-e nde d sig n a l s u p to 2 . 7 g h z o n t h e c l k 1 i n pu t pi n . t h e r f d i v i d e r a l s o s u pp l i e s t h e s y s c lk in pu t t o t h e d d s. b e ca us e t h e d d s o p era t es o n l y u p t o 400 ms ps, de vice f u n c t i on r e q u ir es tha t f o r a n y clk1 sig n al >400 m h z, t h e rf divider m u s t b e en g a g e d . th e rf divider ca n be p r og ra mm ed t o t a k e val u es o f 1, 2, 4, o r 8. th e ra tio f o r th e di vid e r is p r ogra mm e d in t h e co n t r o l r e gis t er . t h e output of t h e d i v i d e r c a n b e route d to t h e i n put of t h e on - c h i p cml d r i v er . f o r lo w e r f r eq uen c y in p u t sign als, i t is p o s s i b le t o us e t h e div i der to di v i de t h e i n pu t sig n a l to t h e cml dr i v er and to us e t h e u n d i v i de d in p u t o f t h e divi der as t h e s y scl k i n p u t t o th e dds, o r vice vers a . i n al l cas e s, t h e s y s c lk t o t h e d d s s h o u l d n o t exce ed 400 ms ps. the o n -chi p phas e f r e q uen c y det e c t o r has tw o dif f er en t i al i n put s , r e f i n ( t he re f e re nc e i n put ) an d c l k 2 ( t he f e e d b a c k or os ci l l a t o r i n p u t). th e s e dif f er en t i al in p u ts c a n b e dr i v e n b y sin g le-e nde d si g n a l s. w h e n doin g s o , t i e t h e u n us e d in pu t thr o ug h a 100 p f ca p a ci t o r t o t h e a n alog s u p p ly (a vd d). the max i m u m sp e e d o f t h e phas e f r e q uen c y de te c t or in p u ts is 200 mh z. e a ch o f th e in p u ts has a b u f f er a nd a divider (m o n refin an d n o n clk2) tha t o p era t es u p t o 655 mh z. i f t h e s i gn al e x ceed s 200 mh z , t h e di vi d e r m u s t be us ed . th e d i v i d e r s are pro g r a m m e d t h rou g h t h e c o n t ro l re g i ste r s an d t a k e an y in teg e r val u e betw een 1 an d 16. the refin in pu t als o has t h e op t i o n o f en g a g i n g a n i n -l i n e os cil l a t o r cir c u i t. en ga g i n g t h is cir c ui t m e an s tha t t h e refi n in p u t can b e dr iv en wi t h a cr y s t a l in t h e ra n g e of 20 mh z refin 30 m h z. the c h a r g e p u m p o u t p u t s a c u r r en t in r e sp o n s e t o a n er r o r sig n a l gener a te d i n t h e phas e f r e q uen c y dete c t o r . th e o u t p u t c u r r en t is p r og ra mme d t h r o ug h b y pl acin g a r e sist o r (cp_r set ) f r o m t h e cp _r s e t pin to g r o u nd . t h e va l u e is dic t a t e d b y set cp_r cp_iout 1.55 = this s e ts t h e cha r g e p u m p r e fer e n c e o u t p u t c u r r en t. als o , a p r og ra mma b l e s c aler m u l t i p lie s t h is b a s e val u e b y a n y in teg e r f r o m 1 t o 8, p r og ra mma b l e t h r o ug h t h e c p c u r r en t s c ale b i ts i n th e c o n t r o l f u n c ti o n r e gi st e r 2, c f r 2 [2: 0 ]. cml driver an o n -chi p c u r r en t m o de logic (cml) dr i v er is also in cl ude d . th i s c m l dr ive r ge ne r a te s ve r y l o w jitte r cl o c k e d ge s . t h e o u t p uts o f t h e c m l dr i v er a r e c u r r en t o u t p u t s t h a t dr i v e p e cl lev e l s w h en t e r m ina t ed in t o a 100 ? lo ad . the co n t in uo us o u t p ut c u r r en t o f t h e dr i v er is p r og ra mm e d b y a t t a chi n g a re s i stor f r om t h e dr v _ r s e t pi n to g r ou n d ( n o m i n a l ly 4 . 0 2 k ? f o r a co n t in uo u s c u r r en t o f 7.2 ma). an op tio n al o n -c hi p c u r r en t p r og ra mming r e sis t o r is ena b le d b y s e t t i n g a b i t in t h e c o n t ro l re g i ste r . t h e r i s i ng e d ge an d f a l l i n g e d g e sl e w r a te s are inde p e n d e n t l y p r o g r a mma b l e to h e l p con t r o l o v ersho o t an d r i n g in g b y t h e a p plica t io n o f su rge c u r r en t d u r i n g r i sin g e d ge a nd fal l in g edge tra n si tio n s (s e e f i gur e 37). th er e is a def a u l t s u rg e c u r r en t o f 7.6 ma o n t h e r i sin g edg e and o f 4.05 ma o n t h e fal l i n g e d g e . bi ts i n t h e con t r o l r e g i s t er ena b le addi t i o n a l r i sin g e d g e and fal l in g e d g e s u rg e c u r r en t, as we l l as dis a b l e t h e defa u l t s u rg e c u r r en t (s e e t h e c o n t r o l reg i st er bi t d e s c r i p t io n s s e c t io n fo r det a i l s). th e c m l dr i v er ca n b e dr i v en b y : ? rf divid e r in put (clk1 dir e c t ly to t h e cm l dr i v er ) ? rf divider o u t p u t ? clk2 in p u t 04947-017 i(t) t ~250ps ~250ps rising edge surge continuous continuous falling edge surge fi gure 37 . ri s i ng ed ge a n d fal l i n g edg e surg e current o u t o f the cml clo c k dr iv er , a s opposed to the st eady stat e co ntinu o us cur r ent
ad9540 rev. a | page 20 of 32 dds a n d d a c f i na l l y , t h e am pl i t u d e w o r d s a r e p i p e d t o a 10 - b i t d a c . b e ca u s e th e d a c i s a sa m p led d a ta s y s t e m , th e o u t p u t i s a r e c o n s t r u c t e d s i n e wa v e tha t n eeds t o b e f i l t e r e d t o tak e high f r eq uen c y i m a g e s o u t o f t h e s p ec tr um. th e d a c i s a curr en t s t e e rin g d a c t h a t i s a v dd refer e nc e d . t o get a me as ur a b le v o l t a g e o u t p u t , t h e d a c o u t p u t s m u s t b e t e r m ina t e d t h r o ug h a lo ad r e s i sto r t o a v d d , typi ca l l y 50 ? . a t p o s i t i ve f u l l s c a l e, io ut s i nks n o c u r r e n t and th e v o l t a g e d r o p a c r o s s th e l o a d r e s i s t o r i s 0 . h o w e v e r , th e iou t o u t p u t s i nk s th e p r o g ra m m ed full - s ca l e o u t p u t cu rr e n t o f th e d a c, c a us i n g t h e max i m u m o u t p ut v o l t ag e dro p acr o s s t h e lo ad r e sist o r . a t neg a t i ve f u l l - s c al e , t h e s i t u a t ion is re vers e d and i o ut sinks t h e f u l l -s c a le c u r r e n t (and g e n e r a t e s t h e maxim u m dr op acr o ss t h e lo ad resist o r ) , w h il e iou t sin k s no c u r r e n t ( a nd ge ne r a te s no vo lt age d r op ) . a t m i d s c a l e , t h e output s s i n k e q u a l a m o u n t s o f cu rr e n t, g e n e ra tin g eq u a l v o l t a g e d r o p s . the p r e c isio n f r e q uen c y division w i t h in t h e d e vice is acco m p lish e d usin g d d s t e chnolog y . th e d d s ca n con t r o l th e dig i t a l phas e r e l a t i o n shi p s b y cl o c k i n g a 48-b i t acc u m u la t o r . the i n cr e m e n t a l val u e lo ade d i n t o t h e acc u m u la t o r , k n o w n as t h e f r e q ue n c y t u nin g w o rd , con t r o ls t h e o v er f l o w ra t e o f t h e acc u m u la t o r . si mi la r t o a s i n e wa ve co m p let i ng a 2 rad i an r e v o l u t i o n , t h e o v er f l o w o f t h e acc u m u la t o r is c y clical in na t u re a nd ge n e r a tes a f u ndam e n t a l f r e q uen c y acco r d i n g to 48 2 ) ( s o f ftw f } 2 w {0 47 ft the ins t an t a n e ous phas e o f t h e sin e w a v e is t h e r efo r e t h e o u t p ut o f t h e phas e acc u m u l a t o r b l o c k. this sig n al ca n b e phas e-o f fs et b y p r o g r a mming a n ad di t i ve di g i t a l phas e t h a t is adde d to e a ch phas e s a m p le comin g o u t o f t h e acc u m u la t o r . t h ese in s t a n ta n e o u s p h a s e v a l u e s a r e th en p i pe d th r o u g h a phas e-t o -am p l i t u de con v ersio n (s o m et i m es c a l l e d a n an g l e- t o - a m pli t ude co n v ersio n o r aa c) b l o c k. this alg o r i t h m fol l o w s a c o s(x) r e la t i o n s h i p , w h er e x is t h e phas e co mi n g o u t o f t h e phas e o f fs et b l o c k, n o r m ali z e d t o 2.
ad9540 rev. a | page 21 of 32 modes of opera tion selectable clock f r equencies and selectable edge delay b e ca us e t h e p r e c isio n dr i v er is i m ple m en t e d usi n g a d d s, i t i s p o ss ibl e to st ore m u lt ipl e cl o c k f r e q u e nc y word s to e n abl e ext e r n al ly swi t cha b le clo c k f r e q uen c ies. th e phas e acc u m u l a t o r r u n s a t a f i xe d f r e q uen c y , acco rdin g to t h e ac t i ve p r o f i l e clo c k f r eq uen c y w o r d . lik e wis e , a n y d e la y a p p l ied t o th e r i sin g a n d fa l l in g e d ges is a st a t ic va l u e t h a t com e s f r o m t h e dela y shif t w o r d o f t h e ac t i v e p r o f i l e . the de vice has eig h t dif f er en t p h a s e / f r eq uen c y p r o f ile s , ea c h w i th i t s o w n 48-b i t c l ock f r e q u e nc y word an d 1 4 - bit d e l a y sh i f t word. pr of i l e s are s e l e c t e d b y a p p l yi n g th e i r d i g i ta l v a l u e s o n th e c l oc k s e le ct p i n s ( p i n s 0 , p i n s1, an d p i n s2). i t is n o t p o ssi b l e t o us e t h e phas e o f fs et o f one prof i l e an d t h e f r e q u e nc y tu n i ng word of a n ot he r . synchr onization modes for multiple de vices i n a d d s sys t em, t h e s y n c _cl k is de r i v e d in t e r n ally f r o m t h e mas t er s y s t em c l o c k, s y sclk, wi t h a 4 di vider . b e ca us e t h e di vider do es n o t p o w e r u p t o a k n o w n st a te, m u l t i p le de vices in a s y ste m mig h t ha ve st ag gere d cl o c k phas e rel a t i ons h i p s , b e c a u s e ea c h d e v i ce ca n po t e n t i a ll y g e n e r a t e th e s y n c _ c l k ri s i n g ed g e f r om an y one of f o ur r i s i ng e d ges of s y s c l k . t h is am bi g u it y c a n be r e sol v e d b y e m p l o y in g di g i t a l syn c hr o n iza t io n log i c t o co n t r o l t h e phas e r e la t i o n s h i p s o f t h e de ri v e d clo c ks a m o n g dif f e r en t de vices in t h e s y s t em. n o t e t h a t th e syn c hr o n iza t i o n f u n c t i o n s in c l uded o n th e ad9540 co n t r o l o n l y th e timin g r e la tio n s h i p s a m o n g dif f e r en t dig i t a l clo c ks. th e y do n o t co m p en s a t e f o r t h e a n al og ti m i n g d e la y o n th e s y s t e m c l oc k d u e t o m i s m a t c h ed p h a s e r e la t i o n s h i p s o n t h e in p u t clock, clk1 (s ee fi g u re 3 8 ) . sysclk dut1 sync_clk dut1 sync_clk dut2 w/o sync_clk aligned sysclk dut2 sync_clk dut2 w/ sync_clk aligned 01 2 30 01 2 3 3 synchronization functions can align digital clock relationships, they cannot deskew the edges of clocks 04947-018 fig u re 3 8 . sy n c hr o n iz at io n fun c t i ons : capab i l i t i es and li mit a t i o n s automatic s y nchroniz ation i n a u t o ma t i c syn c hr o n iza t io n m o de , t h e de vice is place d in sla v e mo de and a u toma t i c a l l y a l ig ns t h e i n te r n a l s y n c _ c l k to a mas t e r s y n c _clk signal, s u p p lie d o n t h e s y n c _in in p u t. w h en t h is b i t i s e n abl e d, t h e st a t u s i s not a v ai l a bl e as an out p ut ; ho we ve r , an out - of -l o c k c o nd it i o n c a n b e d e te c t e d b y re a d i n g c o n t rol f u nc t i o n reg i s t er 1 a n d c h e c kin g t h e s t a t us o f t h e s t a t us_err o r b i t . th e a u t o ma t i c syn c h r o n iza t i o n f u n c t i o n is ena b le d b y s e t t in g t h e c o n t r o l f u n c ti o n r e gi s t e r 1, a u t o m a ti c s y n c h r o n i z a t i o n b i t cfr1[3]. t o em plo y t h is f u n c t i o n a t hig h er c l o c k ra t e s (s yn c_clk > 62.5 mh z, s y scl k > 250 mh z), th e hig h s p e e d syn c ena b le b i t (cfr1[0]) s h o u ld b e s et as w e l l . man ual sync h r onization, h a r d ware cont rolled i n t h i s m o d e , t h e u s e r c o n t ro l s t h e t i m i ng re l a t i onsh ip of t h e s y nc _ c l k w i t h re sp e c t to s y s c l k . whe n h a rdw a re m a n u a l syn c hr o n iz a t io n is ena b le d , t h e s y n c _in/st a t us pin beco m e s a dig i t a l in p u t. f o r each r i sin g edge det e c t e d o n t h e s y n c _in in pu t , t h e de vi ce adv a n c es t h e s y n c _in r i sin g e d g e b y o n e s y scl k p e r i o d . w h e n t h is b i t is ena b le d , t h e st a t us i s not a v ai l a bl e a s an output ; howe ve r , an out - of - l o c k c o n d i t i o n ca n b e dete c t e d b y r e ad in g c o n t r o l f u n c t i o n re g i ster 1 a nd che c k i ng t h e st atu s of t h e st a t u s _ e r ror bit . t h i s s y nc h r o - niza tio n f u n c t i o n is ena b le d b y s e t t in g t h e h a r d wa r e m a n u al s y n c hr o n i z a t ion ena b le bi t cf r1[1]. manual synchronization, so ftware contro lled i n t h i s mo de, t h e us er co n t r o ls t h e t i mi n g r e la t i o n s h i p b e tw e e n s y n c _ c lk a n d s y s c lk th r o u g h so f t w a r e p r ogra m m i n g . w h en t h e s o f t w a r e ma n u al sy n c hr o n iza t io n b i t (cfr1[2]) is s et hig h , t h e s y n c _clk is ad van c ed b y o n e s y sclk c y c l e . on ce t h is o p era t io n is co m p let e , t h e b i t is cle a r e d . the us er ca n s et t h is b i t r e p e a t e d ly t o ad van c e t h e s y nc_cl k r i sin g e d g e m u l t i p le t i m e s. b e ca us e t h e o p e r a t io n do es n o t us e t h e s y n c _in / st a t us pin as a s y n c _i n i n p u t, t h e st a t us sig n a l can b e mo ni to r e d on t h e st a t us p i n d u r i n g t h is op e r a t i o n .
ad9540 rev. a | page 22 of 32 serial port opera t ion an ad9540 s e r i al da t a p o r t co mm unic a t io n c y c l e has tw o phas es. phas e 1 is t h e in st r u c t io n c y cle , wr i t i n g a n inst r u c t io n b y t e t o t h e ad9 540, co in c i den t wi th t h e f i rs t eig h t scl k r i sin g e d ges. th e in st r u c t io n b y t e p r o v ide s t h e a d 95 40 s e r i a l p o r t c o n t ro l l e r w i t h i n f o r m a t i o n re g a rd i n g t h e d a t a t r ans f e r c y cl e, w h i c h i s p h a s e 2 o f t h e co mm unica t io n c y cle . t h e p h as e 1 i n s t r u c t i o n b y t e d e fi n e s t h e s e r i a l addr es s o f t h e r e g i s t er b e in g acces s e d a n d w h e t h e r t h e u p c o m i n g da ta tra n sf er is r e ad o r wr i t e . the f i rs t ei g h t s c lk r i sin g e d g e s o f e a ch co mm unic a t io n c y cle a r e us ed t o wr i te the ins t r u c t io n b y te in t o t h e ad9540. the r e ma ini n g scl k e d g e s a r e fo r p h as e 2 o f t h e c o mm uni c a t io n c y c l e . p h as e 2 is th e ac t u al da ta tra n sf er betw e e n t h e ad9540 a nd t h e sys t e m co n t r o l l er . the n u m b er o f b y t e s t r a n sfer r e d d u r i n g p h as e 2 o f t h e co mm u - n i c a t i on c y cl e i s a f u nc t i on of t h e re g i ste r be i n g a c c e s s ed . f o r e x am p l e, w h e n ac c e ss ing c o n t rol f u nc t i on re g i st e r 2 , w h ich is four b y t e s wide , p h ase 2 r e q u i r es t h a t fo u r b y t e s be t r a n sf err e d . i f a cce s s i n g a fr eq u e n c y tu n i ng w o r d , w h i c h i s s i x by t e s w i d e , p h as e 2 r e q u ir es t h a t six b y t e s be t r a n sfer r e d . af t e r t r a n sfer r i n g al l da t a b y t e s p e r t h e i n s t r u c t ion, t h e co mm uni c a t ion c y cle is co m p let e d . a t the co m p let i o n o f a n y co mm unica t io n c y c l e , t h e ad9540 s e r i al p o r t co n t r o l l er exp e c t s t h e n e xt e i g h t r i si n g sclk e d g e s t o b e t h e inst r u c t io n b y t e o f t h e n e xt comm u n ica t io n c y cle . al l da ta in p u t t o t h e ad9540 is r e g i s t er ed o n t h e r i sin g edg e o f sclk. al l da ta is dr i v en ou t o f t h e ad9540 o n t h e f a l l in g e d g e of s c l k . f i g u re 3 9 t h rou g h f i g u re 4 2 are u s e f u l i n u n d e r s t a n d - in g t h e g e n e ral o p era t ion o f the ad9540 s e r i al p o r t . . 04947-019 i 6 i 5 i 4 i 3 i 2 i 1 d 5 d 4 d 3 d 2 d 1 d 0 i 0 d 7 d 6 i 7 instruction cycle sclk sdi/o data transfer cycle cs fig u re 3 9 . s e r i a l po rt wr it e t i ming c lo ck st a ll l o w 04947-020 i 6 i 5 i 4 i 3 i 2 i 1 i 0 don't care i 7 instruction cycle sclk sdi/o data transfer cycle d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 sdo cs figure 4 0 . 3-w i r e s e ri al p o rt r e ad t i m i ng cl o ck st al l l o w 04947-021 i 6 i 5 i 4 i 3 i 2 i 1 d 5 d 4 d 3 d 2 d 1 d 0 i 0 d 7 d 6 i 7 instruction cycle scl k sdi/o data transfer cycle cs fig u re 4 1 . s e r i a l po rt wr it e t i ming c lo ck st a ll hig h 04947-022 i 6 i 5 i 4 i 3 i 2 i 1 d 5 d 4 d 3 d 2 d 1 d 0 i 0 d 7 d 6 i 7 instruction cycle scl k sdi/o data transfer cycle cs figure 4 2 . 2-w i r e s e ri al p o rt r e ad t i m i ng cl o ck st al l hi g h
ad9540 rev. a | page 23 of 32 instructio n byte the inst r u c t io n b y t e con t a i n s t h e fol l o w in g i n fo r m a t io n. m s b l s b d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r/w b x x a 4 a 3 a 2 a 1 a 0 r/wbb i t 7 o f t h e in st r u c t io n b y t e det e r m i n es w h et h e r a r e ad o r wr i t e da t a t r a n sfer o c c u rs a f t e r t h e in s t r u c t ion b y te wr i t e. log i c 1 in dica t e s a r e ad op era t io n. log i c 0 indica t e s a wr i te op e r a t i o n . x, xb i t 6 an d b i t 5 o f t h e ins t r u c t io n b y t e a r e do n t c a r e . a4, a3, a2, a1, a nd a0bi t 4, bi t 3, bi t 2, bi t 1 , a nd bi t 0 o f t h e in st r u c t io n b y t e det e r m i n e w h ich r e g i st er i s access e d d u r i ng th e da t a tra n s f e r po r t i o n o f th e co m m uni c a t i o n s c y c l e . serial interface port pin description s c l k s e r i a l cl oc k . t h e se rial c l oc k p i n i s u s ed t o s y n c h r o n ize da ta t o a nd f r o m t h e ad9540 a nd t o r u n t h e in t e r n al sta t e machi n es. th e sclk maxim u m f r e q uen c y is 25 mh z. cs chi p s e lec t b a r . cs i s th e a c ti v e lo w in p u t tha t allo w s m o r e tha n o n e de vice o n the s a m e s e r i al co mm u n ic a t io n s lin e . th e s d o p i n an d sdi/o p i n go to a hig h i m p e dance st a t e w h en t h is in p u t is hig h . i f dr i v en hig h d u r i n g an y co mm u n ica t io n s c y cle , t h a t c y cle is susp ende d un t i l cs i s r e a c ti v a t e d lo w . ch i p s e lect ca n be t i ed lo w i n s y s t em s th a t m a i n ta in co n t r o l o f sc l k . s d i/os e r i al da t a i n p u t/ou t p u t . d a ta is al wa ys wr i t ten t o t h e ad9540 o n t h is p i n. h o w e v e r , t h is p i n ca n be u s ed as a b i dir e c t io nal da ta lin e . cfr1[7] co n t r o ls th e conf igura t io n o f t h is p i n. th e de fa u l t v a l u e (0) co nf igur es t h e sd i/o p i n as bi d i re c t i o n a l . s d os e r i al d a ta ou t p u t . d a t a is r e ad f r o m t h is p i n f o r p r o t oco l s th a t use se pa ra t e lin e s f o r tra n s m i t ti n g a n d r e ce i v in g d a t a . w h en t h e ad954 0 op era t es in a s i ng l e b i dir e c t io nal i / o m o d e , th is p i n doe s n o t o u t p u t da ta a n d i s s e t t o a h i g h i m p e dan c e st a te. i/o_reset a hig h s i g n al o n t h is p i n r e s ets t h e i/o p o r t s t a t e machi n es wi t h ou t a f fe c t in g t h e addr es s a b l e r e g i s t ers co n t e n ts . an ac t i v e hig h i n p u t on t h e i/ o _ res e t p i n ca us es t h e c u r r e n t co mm un ic a t io n c y cle t o a b o r t. af t e r i/o_res e t r e t u r n s l o w ( 0 ) , a n o t h e r comm un ic a t io n c y cle ca n b e g i n, st a r t i n g w i t h t h e i n st r u c t i o n b y te w r i t e. n o te t h a t w h e n not i n u s e, t h i s pi n shou l d b e f orc e d l o w , b e c a u s e it f l o a t s to t h e t h re sho l d v a lu e. msb/lsb transfers the ad9540 s e r i al p o r t can s u p p o r t bo t h m o st sig n if ican t b i t (ms b ) f i r s t o r l e as t signif ica n t b i t (ls b ) f i r s t da ta f o r m a t s. t h is f u n c t i o n ali t y is co n t r o l l e d b y t h e ls b f i rs t b i t in c o n t r o l reg i st er 1 (cfr 1[15]). th e def a u l t val u e o f t h is b i t is lo w (ms b f i rs t). w h en cf r1[15] is s et hig h , t h e ad9540 s e r i al p o r t is in ls b f i rs t fo r m a t . the ins t r u c t io n b y te m u st b e wr i t t e n i n t h e f o r m a t indica te d b y cfr1[15]. i f the ad9540 is in ls b f i rst m o de , t h e in st r u c t io n b y t e m u s t b e wr i t ten f r o m ls b t o msb . h o w e v e r , t h e ins t r u c t io n b y te phas e o f t h e co mm uni c a t io n c y c l e s t ill p r eced e s t h e d a ta tra n s f e r c y c l e . f o r m s b f i r s t op e r a t i o n , a l l d a t a w r itte n to ( o r re a d f rom ) t h e ad9540 a r e in ms b f i rs t o r d er . i f the ls b m o de is ac ti v e , al l da ta wr i t ten t o ( o r r e ad f r o m ) th e ad9540 a r e in ls b f i rs t ord e r . cs sclk sdi/o t pre t dsu t sclkw t dhld second bit first bit symbol t pre t sclkw t dsu t dhld min 6ns 40ns 6.5ns 0ns definition cs setup time period of serial data clock (write) serial data setup time serial data hold time 04947- 039 figure 4 3 . t i ming diag ra m f o r d a ta writ e to a d 9 5 4 0 t dv first bit second bit sdi/o sdo sclk cs symbol t dv t sclkr max 40ns 400ns definition data valid time period of serial data clock (read) 04947-040 t sclkr fi gur e 44 . tim i ng di a g r a m f o r da ta re a d fro m ad95 40
ad9540 rev. a | page 24 of 32 register map and description table 4. register map register name (serial address) bit range bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value/ profile [31:24] open 1 open 1 open 1 open 1 open 1 open 1 open 1 status_error 0x00 [23:16] load srr @ i/o_update auto- clear freq. accum. auto- clear phase accum. enable sine output clear freq. accum. clear phase accum. open 1 open 1 0x00 [15:8] lsb first sdi/o input only open 1 open 1 open 1 open 1 open 1 open 1 0x00 control function register 1 (cfr1) (0x00) [7:0] digital power- down pfd input power- down refin cyrstal enable sync_clk out disable auto sync multiple ad9540s software manual sync hardware manual sync high speed sync enable 0x00 [39:32] dac power- down open 1 open 1 open 1 open 1 open 1 internal band gap power- down internal cml driver drv_rset 0x00 [31:24] clock driver rising edge [31:29] clock driver falling edge control [28:26] pll lock detect enable pll lock detect mode 0x00 [23:16] rf divider power- down rf divider ratio[22:21] clock driver power- down clock driver input select [19:18] slew rate control rf div clk1 mux bit 0x78 [15:8] divider n control[15:12] divider m control[11:8] 0x00 control function register 2 (cfr2) (0x01) [7:0] open 1 open 1 cp polarity cp full pd cp quick pd cp current scale[2:0] 0x07 [23:16] rising delta frequency tuning word [23:16] 0x00 [15:8] rising delta frequency tuning word [15:8] 0x00 rising delta frequency tuning word (rdftw) (0x02) [7:0] rising delta frequency tuning word [7:0] 0x00 [23:16] falling delta frequency tuning word [23:16] 0x00 [15:8] falling delta frequency tuning word [15:8] 0x00 falling delta frequency tuning word (fdftw) (0x03) [7:0] falling delta frequency tuning word [7:0] 0x00 [15:8] rising sweep ramp rate [15:8] 0x00 rising sweep ramp rate (rsrr) (0x04) [7:0] rising sweep ramp rate [7:0] 0x00 [15:8] falling sweep ramp rate [15:8] 0x00 falling sweep ramp rate (fsrr) (0x05) [7:0] falling sweep ramp rate [7:0] 0x00
ad9540 rev. a | page 25 of 32 register name (serial address) bit range bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value/ profile [63:56] open 1 phase offset word 0 (pow0) [13:8] 0x00 [55:48] phase offset word 0 (pow0) [7:0] 0x00 [47:40] frequency tuning word 0 (ftw0) [47:40] 0x00 [39:32] frequency tuning word 0 (ftw0) [39:32] 0x00 [31:24] frequency tuning word 0 (ftw0) [31:24] 0x00 [23:16] frequency tuning word 0 (ftw0) [23:16] 0x00 [15:8] frequency tuning word. 0 (ftw0) [15:8] 0x00 profile control register 0 (pcr0) (0x06) [7:0] frequency tuning word 0 (ftw0) [7:0] 0x00 [63:56] open 1 phase offset word 1 (pow1) [13:8] 0x00 [55:48] phase offset word 1 (pow1) [7:0] 0x00 [47:40] frequency tuning word 1 (ftw1) [47:40] 0x00 [39:32] frequency tuning word 1 (ftw1) [39:32] 0x00 [31:24] frequency tuning word 1 (ftw1) [31:24] 0x00 [23:16] frequency tuning word 1 (ftw1) [23:16] 0x00 [15:8] frequency tuning word 1 (ftw1) [15:8] 0x00 profile control register 1 (pcr1) (0x07) [7:0] frequency tuning word 1 (ftw1) [7:0] 0x00 [63:56] open 1 phase offset word 2 (pow2) [13:8] 0x00 [55:48] phase offset word 2 (pow2) [7:0] 0x00 [47:40] frequency tuning word 2 (ftw1) [47:40] 0x00 [39:32] frequency tuning word 2 (ftw2) [39:32] 0x00 [31:24] frequency tuning word 2 (ftw2) [31:24] 0x00 [23:16] frequency tuning word 2 (ftw2) [23:16] 0x00 [15:8] frequency tuning word 2 (ftw2) [15:8] 0x00 profile control register 2 (pcr2) (0x08) [7:0] frequency tuning word 2 (ftw2) [7:0] 0x00 [63:56] open 1 phase offset word 3 (pow3) [13:8] 0x00 [55:48] phase offset word 3 (pow3) [7:0] 0x00 [47:40] frequency tuning word 3 (ftw3) [47:40] 0x00 [39:32] frequency tuning word 3 (ftw3) [39:32] 0x00 [31:24] frequency tuning word 3 (ftw3) [31:24] 0x00 [23:16] frequency tuning word 3 (ftw3) [23:16] 0x00 [15:8] frequency tuning word 3 (ftw3) [15:8] 0x00 profile control register 3 (pcr3) (0x09) [7:0] frequency tuning word 3 (ftw3) [7:0] 0x00 [63:56] open 1 phase offset word 4 (pow4) [13:8] 0x00 [55:48] phase offset word 4 (pow4) [7:0] 0x00 [47:40] frequency tuning word. 4 (ftw4) [47:40] 0x00 [39:32] frequency tuning word 4 (ftw4) [39:32] 0x00 [31:24] frequency tuning word 4 (ftw4) [31:24] 0x00 [23:16] frequency tuning word 4 (ftw4) [23:16] 0x00 [15:8] frequency tuning word 4 (ftw4) [15:8] 0x00 profile control register 4 (pcr4) (0x0a) [7:0] frequency tuning word 4 (ftw4) [7:0] 0x00 [63:56] open 1 phase offset word 5 (pow5) [13:8] 0x00 [55:48] phase offset word 5 (pow5) [7:0] 0x00 [47:40] frequency tuning word 5 (ftw5) [47:40] 0x00 [39:32] frequency tuning word 5 (ftw5) [39:32] 0x00 [31:24] frequency tuning word 5 (ftw5) [31:24] 0x00 [23:16] frequency tuning word 5 (ftw5) [23:16] 0x00 [15:8] frequency tuning word 5 (ftw5) [15:8] 0x00 profile control register 5 (pcr5) (0x0b) [7:0] frequency tuning word 5 (ftw5) [7:0] 0x00
ad9540 rev. a | page 26 of 32 register name (serial address) bit range bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value/ profile [63:56] open 1 phase offset word 6 (pow6) [13:8] 0x00 [55:48] phase offset word 6 (pow6) [7:0] 0x00 [47:40] frequency tuning word 6 (ftw6) [47:40] 0x00 [39:32] frequency tuning word 6 (ftw6) [39:32] 0x00 [31:24] frequency tuning word 6 (ftw6) [31:24] 0x00 [23:16] frequency tuning word 6 (ftw6) [23:16] 0x00 [15:8] frequency tuning word 6 (ftw6) [15:8] 0x00 profile control register 6 (pcr6) (0x0c) [7:0] frequency tuning word 6 (ftw6) [7:0] 0x00 [63:56] open 1 phase offset word 7 (pow7) [13:8] 0x00 [55:48] phase offset word 7 (pow7) [7:0] 0x00 [47:40] frequency tuning word 7 (ftw7) [47:40] 0x00 [39:32] frequency tuning word 7 (ftw7) [39:32] 0x00 [31:24] frequency tuning word 7 (ftw7) [31:24] 0x00 [23:16] frequency tuning word 7 (ftw7) [23:16] 0x00 [15:8] frequency tuning word 7 (ftw7) [15:8] 0x00 profile control register 7 (pcr7) (0x0d) [7:0] frequency tuning word 7 (ftw7) [7:0] 0x00 1 in all cases, open bits must be written to 0.
ad9540 rev. a | page 27 of 32 control register bit descriptions control function register 1 (cfr1) this control register is comprised of four bytes that must be written during a write operation involving cfr1. cfr1 is used to control various functions, features, and operating modes of the ad9540. the functionality of each bit is described below. in general, the bit is named for the function it serves when the bit is set. cfr1[31:25] open unused locations. write a logic 0. cfr1[24] status_error (read only) when the device is operating in automatic synchronization mode or hardware manual synchronization mode the sync_in/status pin behaves as the sync_in. to determine whether or not the pll has become unlocked while in synchronization mode, this bit serves as a flag to indicate that an unlocked condition has occurred within the phase frequency detector. once set, the flag stays high until it is cleared by a readback of the value even though the loop might have relocked. readback of the cfr1 register clears this bit. cfr1[24] = 0 indicates that the loop has maintained lock since the last readback. cfr1[24] = 1 indicates that the loop became unlocked at some point since the last readback of this bit. cfr1[23] load sweep ramp rate at i/o_update, also known as load srr @ i/o_update the sweep ramp rate is set by entering a value to a down- counter that is clocked by the sync_clk. each time a new step is taken in the linear sweep algorithm, the ramp rate value is passed from the linear sweep ramp rate register to this down- counter. when set, cfr1[23] enables the user to force the part to restart the countdown sequence for the current linear sweep step by toggling the i/o_update pin. cfr1[23] = 0 (default). the linear sweep ramp rate countdown value is loaded only upon completion of a countdown sequence. cfr1[23] = 1. the linear sweep ramp rate countdown value is reloaded, if an i/o_update signal is sent to the part during a sweep. cfr1[22] auto-clear frequency accumulator this bit enables the auto clear function for the frequency accumulator. the auto clear function serves as a clear and release function for the frequency accumulator. this performs the linear sweep operation that then begins sweeping from a known value of ftw0. cfr1[22] = 0 (default). issuing an i/o_update has no effect on the current state of the frequency accumulator. cfr1[22] = 1. issuing an i/o_update signal to the part clears the current contents of the frequency accumulator for one sync- clock period. cfr1[21] auto clear phase accumulator this bit enables the auto clear function for the phase accumulator. the auto clear function serves as a reset function for the phase accumulator, which then begins accumulating from a known phase value of 0. cfr1[21] = 0 (default). issuing an i/o_update has no effect on the current state of the phase accumulator. cfr1[21] = 1. issuing an i/o_update clears the current contents of the phase accumulator for one sync_clk period. cfr1[20] enable sine output two different trigonometric functions can be used to convert the phase angle to an amplitude value, cosine, or sine. this bit selects the function used. cfr1[20] = 0 (default). the phase-to-amplitude conversion block uses a cosine function. cfr1[20] = 1. the phase-to-amplitude conversion block uses a sine function. cfr1[19] clear frequency accumulator this bit serves as a static clear, or a clear-and-hold bit for the frequency accumulator. it prevents the frequency accumulator from incrementing the value as long as it is set. cfr1[19] = 0 (default). the frequency accumulator operates normally. cfr1[19] = 1. the frequency accumulator is cleared and held at 0. cfr1[18] clear phase accumulator this bit serves as a static clear, or a clear-and-hold bit for the phase accumulator. it prevents the phase accumulator from incrementing the value as long as it is set. cfr1[18] = 0 (default). the phase accumulator operates normally. cfr1[18] = 1. the phase accumulator is cleared and held at 0. cfr1[17:16] open unused locations. write a logic 0. cfr1[15] lsb first serial data mode the serial data transfer to the device can be either msb first or lsb first. this bit controls that operation.
ad9540 rev. a | page 28 of 32 cfr1[15] = 0 (default). serial data transfer to the device is in msb first mode. cfr1[15] = 1. serial data transfer to the device is in lsb first mode. cfr1[14] sdi/o input only (3-wire serial data mode) the serial port on the ad9540 can act in 2-wire mode (sclk and sdi/o) or 3-wire mode (sclk, sdi/o, and sdo). this bit toggles the serial port between these two modes. cfr1[14] = 0 (default). serial data transfer to the device is in 2-wire mode. the sdi/o pin is bidirectional. cfr1[14] = 1. serial data transfer to the device is in 3-wire mode. the sdi/o pin is input only. cfr1[13:8] open unused locations. write a logic 0. cfr1[7] digital power-down this bit powers down the digital circuitry not directly related to the i/o port. the i/o port functionality is not suspended, regardless of the state of this bit. cfr1[7] = 0 (default). digital logic operating as normal. cfr1[7] = 1. all digital logic not directly related to the i/o port is powered down. internal digital clocks are suspended. cfr1[6] phase frequency detector input power-down this bit controls the input buffers on the phase frequency detector. it provides a way to gate external signals from the phase frequency detector. cfr1[6] = 0 (default). phase frequency detector input buffers are functioning normally. cfr1[6] = 1. phase frequency detector input buffers are powered down, isolating the phase frequency detector from the outside world. cfr1[5] refin crystal enable the ad9540 phase frequency detector has an on-chip oscillator circuit. when enabled, the reference input to the phase fre- quency detector (refin/ refin ) can be driven by a crystal. cfr1[5] = 0 (default). the phase frequency detector reference input operates as a standard analog input. cfr1[5] = 1. the reference input oscillator circuit is enabled, allowing the use of a crystal for the reference of the phase frequency detector. cfr1[4] sync_clk disable if synchronization of multiple devices is not required, the spectral energy resulting from this signal can be reduced by gating the output buffer off. this function gates the internal clock reference sync_clk (sysclk 4) off of the sync_out pin. cfr1[4] = 0 (default). the sync_clk signal is present on the sync_out pin and is ready to be ported to other devices. cfr1[4] = 1. the sync_clk signal is gated off, putting the sync_out pin into a high impedance state. cfr1[3] automatic synchronization one of the synchronization modes of the ad9540 forces the dds core to derive the internal reference from an external reference supplied on the sync_in pin. for details on synchronization modes for the dds core, see the synchronization modes for multiple devices section. cfr1[3] = 0 (default). the automatic synchronization function of the dds core is disabled. cfr1[3] = 1. the automatic synchronization function is on. the device is slaved to an external reference and adjusts the internal sync_clk to match the external reference that is supplied on the sync_in input. cfr1[2] software manual synchronization rather than relying on the part to automatically synchronize the internal clocks, the user can program the part to advance the internal sync_clk one system clock cycle. this bit is self clearing and can be set multiple times. cfr1[2] = 0 (default). the sync_clk stays in the current timing relationship to sysclk. cfr1[2] = 1. the sync_clk advances the rising and falling edges by one sysclk cycle. this bit is then self-cleared. cfr1[1] hardware manual synchronization similar to the software manual synchronization (cfr1[2]), this function enables the user to advance the sync_clk rising edge by one system clock period. this bit enables the sync_in/status pin as a digital input. once enabled, every rising edge on the sync_in input advances the sync_clk by one sysclk period. while enabled, the status signal is not available on an external pin. however, loop out-of-lock events trigger a flag in the control register cfr1[24].
ad9540 rev. a | page 29 of 32 cfr1[1] = 0 (default). the hardware manual synchronization function is disabled. either the part is outputting the status (cfr1[3] = 0) or it is using the sync_in to slave the sync_clk signal to an external reference provided on sync_in (cfr1[3] = 1). cfr1[1] = 1. the sync_in/status pin is set as a digital input. each subsequent rising edge on this pin advances the sync_clk rising edge by one sysclk period. cfr1[0] high speed synchronization enable bit this bit enables extra functionality in the autosynchronization algorithm, which enables the device to synchronize high speed clocks (sync_clk > 62.5 mhz). cfr1[0] = 0 (default). high speed synchronization is disabled. cfr1[0] = 1. high speed synchronization is enabled. control function register 2 (cfr2) the control register 2 is comprised of five bytes, that must be written during a write operation involving cfr2. with some minor exceptions, the cfr2 primarily controls analog and timing functions on the ad9540. cfr2[39] dac power-down bit this bit powers down the dac portion of the ad9540 and puts it into the lowest power dissipation state. cfr2[39] = 0 (default). dac is powered on and operating. cfr2[39] = 1. dac is powered down and the output is in a high impedance state. cfr2[38:34] open unused locations. write a logic 0. cfr2[33] internal band gap power-down to shut off all internal quiescent current, the band gap needs to be powered down. this is normally not done because it takes a long time (~10 ms) for the band gap to power up and settle to its final value. cfr2[33] = 0. even when all other sections are powered down, the band gap is powered up and is providing a regulated voltage. cfr2[33] = 1. the band gap is powered down. cfr2[32] internal cml driver drv_rset to program the cml driver output current, a resistor must be placed between the drv_rset pin and ground. this bit enables an internal resistor to program the output current of the driver. cfr2[32] = 0 (default). the drv_rset pin is enabled, and an external resistor must be attached to the cp_rset pin to program the output current. cfr2[32] = 1. the cml current is programmed by the internal resistor and ignores the resistor on the drv_rset pin. cfr2[31:29] clock driver rising edge these bits control the slew rate of the rising edge of the cml clock driver output. when these bits are on, additional current is sent to the output driver to increase the rising edge slew rate capability. table 5 describes how the bits increase the current. the additional current is on only during the rising edge of the waveform for approximately 250 ps, not during the entire transition. table 5. cml clock driver rising edge slew rate control bits and associated surge current cfr2[31] = 1 7.6 ma cfr2[30] = 1 3.8 ma cfr2[29] = 1 1.9 ma cfr2[28:26] clock driver falling edge control these bits control the slew rate of the falling edge of the cml clock driver output. when these bits are on, additional current is sent to the output driver to increase the rising edge slew rate capability. table 6 describes how the bits increase the current. the additional current is on only during the rising edge of the waveform, for approximately 250 ps, not during the entire transition. table 6. cml clock drive falling edge slew rate control bits and associated surge current cfr2[28] = 1 5.4 ma cfr2[30] = 1 2.7 ma cfr2[29] = 1 1.35 ma cfr2[25] pll lock detect enable this bit enables the sync_in/status pin as a lock detect output for the pll. cfr2[25] = 0 (default).the status_detect signal is disabled. cfr2[25] = 1. the status_detect signal is enabled. cfr2[24] pll lock detect mode this bit toggles the modes of the pll lock detect function. the lock detect can either be a status indicator (locked or unlocked) or it can indicate a lead-lag relationship between the two phase frequency detector inputs.
ad9540 rev. a | page 30 of 32 cfr2[24] = 0 (default). the lock detect acts as a status indicator (pll is locked 0 or unlocked 1). cfr2[24] = 1. the lock detect acts as a lead-lag indicator. a 1 on the status pin means that the clk2 pin lags the reference. a 0 means that the clk2 pin leads the reference. cfr2[23] rf divider power-down this bit powers down the rf divider to save power when not in use. cfr2[23] = 0 (default). the rf divider is on. cfr2[23] = 1. the rf divider is powered down and an alternate path between the clk1 inputs and sysclk is enabled. cfr2[22:21] rf divider ratio these two bits control the rf divider ratio (r). cfr2[22:21] = 11 (default). rf divider r = 8. cfr2[22:21] = 10. rf divider r = 4. cfr2[22:21] = 01. rf divider r = 2. cfr2[22:21] = 00. rf divider r = 1. note that this is not the same as bypassing the rf divider. cfr2[20] clock driver power-down this bit powers down the cml clock driver circuit. cfr2[20] =1 (default). the cml clock driver circuit is powered down. cfr2[20] = 0. the cml clock driver is powered up. cfr2[19:18] clock driver input select these bits control the mux on the input for the cml clock driver. cfr2[19:18] = 00. the cml clock driver is disconnected from all inputs (and does not toggle). cfr2[19:18] = 01. the cml clock driver is driven by the clk2 input pin. cfr2[19:18] = 10 (default). the cml clock driver is driven by the output of the rf divider. cfr2[19:18] = 11. the cml clock driver is driven by the input of the rf divider cfr2[17] slew rate control bit even without the additional surge current supplied by the rising edge slew rate control bits and the falling edge slew rate control bits, the device applies a default 7.6 ma surge current to the rising edge and a 4.05 ma surge current to the falling edge. this bit disables all slew rate enhancement surge current, including the default values. cfr2[17] = 0 (default). the cml driver applies default surge current to rising and falling edges. cfr2[17] = 1. driver applies no surge current during transitions. the only current is the continuous current. cfr2[16] rf divider clk1 mux this bit toggles the mux to control whether the rf divider output or input is supplying sysclk to the device. cfr2[16] = 0 (default). the rf divider output supplies the dds sysclk. cfr2[16] = 1. the rf divider input supplies the dds sysclk (bypass the divider). note that regardless of the condition of the configuration of the clock input, the dds sysclk must not exceed the maximum rated clock speed. cfr2[15:12] clk2 divider (n) control bits these four bits set the clk2 divider (n) ratio where n is a value = 1 to 16, and cfr2[15:12] = 0000 means that n = 1 and cfr2[15:12] = 1111 means that n = 16 or simply, n = cfr2[15:12] + 1. table 7. clk2 divider values (n) cfr2[15:12] n cfr2[15:12] n 0000 1 1000 9 0001 2 1001 10 0010 3 1010 11 0011 4 1011 12 0100 5 1100 13 0101 6 1101 14 0110 7 1110 15 0111 8 1111 16 cfr2[11:8] refin divider (m) control bits these 4 bits set the refin divider (m) ratio where the m = 1 to 16 and cfr2[11:8] = 0000 means that m = 1, and cfr2[11:8] = 1111 means that m = 16 or m = cfr2[11:8] + 1. table 8. refin input divider values (m) cfr2[15:12] m cfr2[11:8] m 0000 1 1000 9 0001 2 1001 10 0010 3 1010 11 0011 4 1011 12 0100 5 1100 13 0101 6 1101 14 0110 7 1110 15 0111 8 1111 16
ad9540 rev. a | page 31 of 32 cfr2[7:6] open unused locations. write a logic 0. cfr2[5] cp polarity this bit sets the polarity of the charge pump in response to a ground referenced or a supply referenced vco. cfr2[5] = 0 (default). the charge pump is configured to operate with a supply referenced vco. if clk2 lags refin, the charge pump attempts to drive the vco control node voltage higher. if clk2 leads refin, the charge pump attempts to drive the vco control node voltage lower. cfr2[5] = 1. the charge pump is configured to operate with a ground referenced vco. if clk2 lags refin, the charge pump attempts to drive the vco control node voltage lower. if clk2 leads refin, the charge pump attempts to drive the vco control node voltage higher. cfr2[4] charge pump full power-down this bit, when set, puts the charge pump into a full power-down mode. cfr2[4] = 0 (default). the charge pump is powered on and operating normally. cfr2[4] = 1. the charge pump is powered down completely. cfr2[3] charge pump quick power-down rather than power down the charge pump, which have a long recovery time, a quick power-down mode that powers down only the charge pump output buffer is included. though this does not reduce the power consumption significantly, it does shut off the output to the charge pump and allows it to come back on rapidly. cfr2[3] = 0 (default). the charge pump is powered on and operating normally. cfr2[3] = 1. the charge pump is on and running, but the output buffer is powered down. cfr2[2:0] charge pump current scale a base output current from the charge pump is determined by a resistor connected from the cp_rset pin to ground (see the pll circuitry section). however, it is possible to multiply the charge pump output current by a value from 1:8 by program- ming these bits. the charge pump output current is scaled by cfr2[2:0] +1. cfr2[2:0] = 000 (default) scale factor = 1 to cfr2[2:0] = 111 (8).
ad9540 rev. a | page 32 of 32 outline dimensions pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 fig u re 4 5 . 48-l e ad lead f r a m e chip s c a l e pa ck ag e [lfcs p _v q] 7 mm 7 m m b o d y , v e ry th in qu ad (cp-48-1) dim e nsio ns sho w n i n mi ll im e t er s ordering guide model t e mper a t ur e r a nge p a ck age descri ption p a ck age o p tion ad9540bcp z 1 ?40c to +85c 48-l e ad l e ad f r ame chip s c ale p a ck age [lfcsp_vq ] cp -48-1 ad9540bcp z - re el7 1 ?40c to +85c 48-l e ad l e ad f r ame chip s c al e p a ck age [lfcsp_vq ] t a pe and reel cp -48-1 a d 9 5 4 0 / p c b e v alua t i o n boar d a d 9 5 4 0 - v c o / p c b e v alua tion boar d 1 z = pb-free part. ?2006 analo g devi ces, inc. all rights reserve d . tra d em ar ks and registered tra d emar ks are the prop erty of their respective o w ners . d04947-0-2/06(a)

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